The invention relates to an efficient topography for a CMOS microcomputer including an eight bit CMOS microprocessor, 4096 bytes of ROM, 192 bytes of RAM, eight chip select outputs, two 16 bit timers, a serial interface bus circuit configured for connection to a token passing local area network, a UART, a watchdog timer with restart interrupt capability, 22 priority encoded interrupts, a toolbox emulation interface, real time clock features, a bus control register for external memory bus control, and interface circuitry for I/O devices.
U.S. Pat. Nos. 4,652,992 and 4,739,475 fully describe the topography and logic circuitry of commercially available processors known as the W65C02 and W65C816 microprocessors, respectively. Microprocessors generally contain an internal address bus, an internal data bus, a number of registers including an accumulator, a program counter, an internal data latch, stack pointer registers, index registers, an arithmetic logic unit, an instruction register, a status register, and instruction decoding circuitry, register transfer logic, and data buffer latches and address latches. Microprocessors do not ordinarily contain additional components that are needed in a microcomputer system, such as a read only memory for storing programs, a random access memory for storing variables and data, timers, UART's, I/O functions, priority interrupt systems and the like. However, with the wide availability and commercial success of quite a number of microprocessors, various suppliers have begun using commercially available microprocessor designs as the "cores" of larger microcontrollers or microcomputers on single silicon chips that include not only the microprocessor, but some or all of the above-mentioned components and others.
The foregoing integrated circuit topography design considerations and constraints make it a considerable challenge to design a microcomputer or microcontroller utilizing an already designed layout for the microprocessor "core" section. Positioning of the core microprocessor, the ROM, RAM, UART, timers, bus control register, and interface circuitry, etc. must be accomplished in such a way as to allow the microprocessor to interface easily on a printed circuit board with other ASIC's (applications specific integrated circuits) designed by the user to implement a larger system. Difficult tradeoffs must be established between the often opposing objectives of (1) minimizing total semiconductor area occupied by the microcomputer and (2) making connection to many leads of the microcomputer which have to be located in certain positions for reasons that have nothing to do with minimizing microcomputer chip area.
The closest prior art known to me is the W65C124 microcontroller, which I designed now and market through my company, The Western Design Center, Inc. of Mesa, Ariz. The function and topography of the W65C124 did not succeed in adequately meeting the objectives of a general purpose microcomputer that can be easily interfaced to a wide variety of ASIC's or other circuitry likely to be required by a user in implementing a larger microcomputer system. The development of the WC65124 circuit and attempts to use that as a "core" microcomputer for even larger microcomputer systems led to the present invention, which is an expanded capability microcomputer that provides an optimum amount of microcomputer function in a relatively small amount of silicon chip area, and provides an optimum interfacing configuration to external memory, I/O, register, interrupt, and serial communications circuitry with minimum chip area and minimum difficulty in routing conductors to various external circuits.
There is a presently unmet need for an efficient topography for a microcomputer including the W65C02's or other CMOS microprocessor and a variety of peripheral ROM, RAM, UART, priority interrupt, and other functions on a single chip. There also is a need for a microcontroller topography which can be efficiently used as the "core" of a larger monolithic microcomputer integrated circuit.